1. Field of the Invention
The disclosure generally relates to an apparatus, and more particularly, relates to an apparatus for duty cycle calibration.
2. Description of the Related Art
A frequency doubler is a common component in a digital circuit and in modern frequency synthesizers to reduce phase noise. Ideally, the frequency doubler is configured to generate an output clock signal in response to an input clock signal, wherein the frequency of the output clock signal is exactly two times greater than that of the input clock signal.
As a matter of fact, the input clock signal often has duty cycle errors, leading to reference spurs in the frequency domain and degrading performance of the associated analog/digital circuits. Accordingly, there is a need to design a new apparatus for duty cycle calibration.